EDA charter members of the program include: Axis Systems, Inc.; Get2Chip, Inc.; Magma Design Automation, Inc.; Monterey Design Systems, Inc.; Novas Software; Sequence Design, Inc.; Silicon Perspective Corporation; and Tera Systems, Inc. Intellectual Property (IP) suppliers Nurlogic Designs, Inc.and Virtual Silicon Technology, Inc. have also become members. Additional members will be announced shortly.

"Verplex FormaLinks provides an independent means for other third-party vendors to test and verify that their next-generation software is producing correct results," remarks C. Michael Chang, president and CEO of Verplex. "There is a growing trend of companies taking advantage of this program to use Verplex software as a quality assurance metric."

The Verplex FormaLinks Program
The Verplex FormaLinks program lets vendors provide their customers with an integrated, quality design and verification flow from early design stages at the register-transfer level (RTL) to final timing closure. Partners work closely with Verplex to provide mutual customers with a seamless, interoperable design and verification flow.

Additionally, the Verplex FormaLinks program gives vendors an independent verification measure, a crucial step to minimize real design problems and thereby maximize designer confidence in the vendors' products.

"By using Axis' Xtreme™ emulation and Xcite™ simulation acceleration tools to verify a complete system, along with Verplex's equivalence checker to verify the design implementation of each of the chips, designers can increase their overall verification productivity by orders of magnitude over traditional methods," explains Steve Wang, vice president of marketing at Axis Systems. "We are happy to join the Verplex FormaLinks Program to promote our joint methodology."

"We found that Verplex's equivalence checker shares the superior accuracy, exceptional speed and vast capacity of VOLARE™, our SOC multi-level synthesis platform," notes Lauro Rizzatti, director of product marketing at Get2Chip. "Combining our state-of-the-art SOC synthesis technology with the state-of-the-art formal analysis of Verplex, we can guarantee fast and accurate functional convergence between the register-transfer level and the gate-level netlist of complex multi-million gates SOC designs."

Says Bob Smith, vice president of product marketing at Magma: "Magma's Blast Fusion™ and Blast Chip™ products perform extensive logic optimization concurrently with the physical implementation design flow. It is absolutely critical that the correct design functionality is maintained from RTL to silicon. Verplex provides a fast, reliable and independent means to ensure the functional correctness of designs in addition to Magma's own built in checking tool."

"Having Verplex Systems as our endorsed verification partner allows inter operable flows for our customers to verify logic transformations necessary in our Sonar™ and Dolphin™ products to meet functional implementations" describes Dave Reed, vice president of marketing at Monterey Design Systems®. "We see formal verification as an efficient and effective part of today's complex SOC design flows."

"Verification consists of both detection and debug," maintains Scott Sandler, Chief Executive Officer of Novas Software Inc. "Verplex and Novas have cooperated for years to provide mutual customers the best way to detect bugs with formal verification, and the means to locate, isolate and understand why they occur with the industry-standard Debussy total debug system. Joining the Verplex FormaLinks Program adds one more dimension to our work together, and underscores Novas' commitment to open systems and cooperation within the EDA industry."

"Library validation is a critical part of any design effort," begins Jeff Hayashi, director of ASIC Services at Nurlogic. "At NurLogic, we pride ourselves on our qualification validation process across all of our IP offerings. We provide customers with validated libraries by utilizing Verplex verification as part of our methodology."

Kevin Walsh, vice president of product management at Sequence Design, adds: "Verplex offers a very fast, high-capacity verification solution to multi-million gate designs. Sequence customers are already using Verplex as a golden verification step as they tackle difficult timing and signal integrity problems."

"Silicon Perspective's First Encounter™ creates an accurate full-chip physical prototype quickly for the largest SOC designs," states Michel Courtoy, vice president of marketing for Silicon Perspective. "We have used Verplex's equivalence checker extensively and recommend it to our customers because we found the same qualities of quickness and high capacity in this software." "Tera Systems fully supports Verplex's FormaLinks Partners Program because it gives the industry the confidence it needs to adopt second generation flows involving preemptive analysis," observes Mark Miller, vice president of marketing and business development.

"Virtual Silicon Technology has a tradition of providing semiconductor intellectual property that is proven to work in silicon," affirms John Ford, vice president of marketing. "Working with leading verification technology providers like Verplex ensures that tradition will continue."

For more information on the Verplex FormaLinks Program, contact Tom Senna, Verplex business development VP, at (408) 586-0392 or via email at tomsenna@verplex.com.

About Verplex
Verplex Systems Inc. is an electronic design automation (EDA) company focusing on delivery of the highest speed, highest capacity and easiest to use formal verification products for complex system-on-chip (SOC) design. Founded in 1997, it is privately held and funded by leading venture capital firms. Corporate headquarters is located at 300 Montague Expressway, Suite 100, Milpitas, Calif. 95035. Telephone: (408) 586-0300. Facsimile: (408) 586-0230. Email: info@verplex.com. Online information is found at its web site: http://www.verplex.com.